1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection device and a related circuit, and more particularly, to an ESD protection device using only two substrate-triggered silicon-controlled rectifiers (STSCRs) and a related circuit.
2. Description of the Prior Art
Electrostatic discharge (ESD) protection has been a very important reliability issue in integrated circuits (ICs). To prevent the ICs from being damaged during ESD stresses, ESD protection circuits are needed for all input/output (I/O) pins. However, the ESD protection circuits inevitably introduce negative impacts to RF performance due to their parasitic capacitance. As the operating frequency of RF circuits increases, performance degradation due to ESD protection circuits becomes more serious. Silicon-controlled rectifier (SCR) is demonstrated to be suitable for ESD protection design for RF ICs, because it has both high ESD robustness and low parasitic capacitance under a small layout area.
Besides positive-to-VSS mode (PS-mode), positive-to-VDD mode (PD-mode), negative-to-VSS mode (NS-mode) and negative-to-VDD (ND-mode) ESD stresses, there is an additional pin-to-pin ESD stress, which is specified in the standards for the analog or RF circuits with differential input stages so as to verify the ESD robustness of the differential analog or RF input pins. During the pin-to-pin ESD stresses, the positive or negative ESD voltage is applied to one of the differential input pads with the other differential input pad relatively grounded. During such a pin-to-pin ESD stress, all the other pins including the VDD and VSS pins are floating. Please refer to FIG. 1. FIG. 1 is a circuit diagram illustrating an ESD current path during pin-to-pin ESD stresses in the differential input stage of an RF circuit. As shown in FIG. 1, if the connection between the two differential input pads 10, 12 and VDD or VSS power terminal has a long metal line, the gate oxides of the metal oxide semiconductor (MOS) transistors 14, 16 in the differential input stage 18 will be easily damaged by ESD current IESD indicated by a dot line shown in FIG. 1. In addition, the pin-to-pin ESD stress is critical for the differential input stage 18 in CMOS processes because the differential input pads 10, 12 are often connected to the gate electrodes of the MOS transistors 14, 16 in a differential pair. When one of the differential input pads 14 is zapped by ESD with the other differential input pad 16 grounded, the ESD voltage must be quickly clamped in order not to damage the gate oxide of MOS transistors 14, 16. With the advance of CMOS processes, the gate oxide breakdown voltage continuously decreases.